1. Field of the Invention
This invention relates to a semiconductor memory device and a method of controlling the same. More specifically, this invention relates to a nonvolatile semiconductor memory device with MOS transistors each having a floating gate and a control gate.
2. Description of the Related Art
NOR and NAND flash memories have been widely used as nonvolatile semiconductor memory devices.
In recent years, a flash memory combining the features of the NOR flash memory and the NAND flash memory has been proposed. This type of flash memory has been disclosed in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8-V-Only Application,” Non-Volatile Semiconductor Memory Workshop 4.1, 1997. A flash memory of this type (hereinafter, referred to as a 2Tr flash memory) has memory cells each of which includes two MOS transistors. In such a memory cell, one MOS transistor, which functions as a nonvolatile memory section, includes a control gate and a floating gate and is connected to a bit line. The other MOS transistor, which is connected to a source line, is used to select a memory cell.
In a semiconductor memory, a bit line is precharged or discharged, thereby reading the data. At this time, if the bit line is not precharged or discharged sufficiently, the data can be read erroneously. A method of solving this problem has been proposed in, for example, Nobuyuki O., et al., “Circuit Techniques for 1.5-V Power Supply Flash Memory,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 8, August, 1997, pp. 1217-1230 and Rino M., et al., “The Flash Memory Read Path: Building Blocks and Critical Aspects,” PROCEEDINGS OF THE IEEE, Vol. 91, No. 4, April, 2003, pp. 537-553.
However, these methods have a problem: erroneous reading cannot be dealt with sufficiently by, for example, a 2Tr flash memory. In a 2Tr flash memory, there is a channel capacitance in a bit line even when the word line potential is zero. In addition, disturbance in a write or a read operation can make the threshold value of the memory cell fluctuate. As a result, even if a replica circuit is provided, it is difficult to perform control to keep the precharge time and discharge time constant.